The present invention relates generally to integrated circuits. More particularly, the present invention relates to an improved apparatus and method for providing a high speed linear feedback shift register.
The use of linear feedback shift registers is well known in integrated circuit technology. Linear feedback shift registers may be used in a number of applications. For example, a linear feedback shift register may be used to implement a clock divider circuit. A clock divider circuit is used to divide a master clock signal to obtain a different frequency clock signal.
Prior art linear feedback shift registers typically use additional logic circuitry to perform auxiliary functions. For example, when a linear feedback shift register is used as a counter, additional logic circuitry must be used to reset the counter.
It would be desirable to have a linear feedback shift register that would not need to employ additional logic circuitry of the type used in prior art devices.
It would also be desirable to have a linear feedback shift register that was capable of operating as a counter that did not need to be reset.
It would also be desirable to have a linear feedback shift register that was capable of operating at a faster rate than prior art linear feedback shift registers.
The present invention is directed to an apparatus and method for providing a high speed linear feedback shift register (LFSR).
An advantageous embodiment of the present invention comprises a high speed linear feedback shift register that substantially comprises only multiplexer flip flops. The multiplexer gate on the input of each flip flop is the only gate between each flip flop of the LFSR of the present invention. This feature increases the speed of the LFSR of the present invention to a level that is approximately twenty percent (20%) faster than the speed of prior art linear feedback shift registers.
It is an object of the present invention to provide an apparatus and method for providing a high speed linear feedback shift register that does not need to employ additional logic circuitry of the type used in prior art linear feedback shift registers.
It is another object of the present invention to provide an apparatus and method for providing a high speed linear feedback shift register that is capable of operating as a counter that does not need to be reset.
It is also an object of the present invention to provide an apparatus and method for providing a high speed linear feedback shift register that is capable of operating at a faster rate than prior art linear feedback shift registers.
It is still another object of the present invention to provide an apparatus and method for providing a high speed linear feedback shift register for a clock divider for a high speed phase locked loop.
It is yet another object of the present invention to provide an apparatus and method for a high speed linear feedback shift register that does not require multiple stages of logic circuitry to detect an end condition.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the Detailed Description of the Invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject matter of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the Detailed Description of the Invention, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: The terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprisexe2x80x9d and derivatives thereof, mean inclusion without limitation, the term xe2x80x9corxe2x80x9d is inclusive, meaning xe2x80x9cand/orxe2x80x9d; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, to bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontroller,xe2x80x9d xe2x80x9cprocessor,xe2x80x9d or xe2x80x9capparatusxe2x80x9d means any device, system or part thereof that controls at least one operation. Such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document. Those of ordinary skill should understand that in many instances (if not in most instances), such definitions apply to prior, as well as future uses of such defined words and phrases.